用Verilog语言写的三分频电路方法一:上升沿触发的分频设计module three(clkin clkout)input clkin定义输入端口output clkout定义输出端reg [1:0] step1 stepalways (posedge clkin)begincase (step)2b00: step<=2b012b01: step<=2b102b10: step<=2b0